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09/12/2023
RackBlox: A Software-Defined Rack-Scale Storage System with Network-Storage Co-Design
Software-defined networking (SDN) and software-defined flash (SDF) have ...
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01/06/2023
CHARM: Composing Heterogeneous Accelerators for Matrix Multiply on Versal ACAP Architecture
Dense matrix multiply (MM) serves as one of the most heavily used kernel...
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10/17/2022
Extensible Proxy for Efficient NAS
Neural Architecture Search (NAS) has become a de facto approach in the r...
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10/17/2022
What Makes Convolutional Models Great on Long Sequence Modeling?
Convolutional models have been widely used in multiple domains. However,...
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07/22/2022
HiKonv: Maximizing the Throughput of Quantized Convolution With Novel Bit-wise Management and Computation
Quantization for CNN has shown significant progress with the intention o...
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07/03/2022
Chimera: A Hybrid Machine Learning Driven Multi-Objective Design Space Exploration Tool for FPGA High-Level Synthesis
In recent years, hardware accelerators based on field-programmable gate ...
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12/28/2021
HiKonv: High Throughput Quantized Convolution With Novel Bit-wise Management and Computation
Quantization for Convolutional Neural Network (CNN) has shown significan...
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10/26/2021
YOLO-ReT: Towards High Accuracy Real-time Object Detection on Edge GPUs
Performance of object detection models has been growing rapidly on two m...
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08/04/2021
Generic Neural Architecture Search via Regression
Most existing neural architecture search (NAS) algorithms are dedicated ...
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07/24/2021
ScaleHLS: A New Scalable High-Level Synthesis Framework on Multi-Level Intermediate Representation
High-level synthesis (HLS) has been widely adopted as it significantly i...
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07/09/2021
WinoCNN: Kernel Sharing Winograd Systolic Array for Efficient Convolutional Neural Network Acceleration on FPGAs
The combination of Winograd's algorithm and systolic array architecture ...
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05/10/2021
Skew-Oblivious Data Routing for Data-Intensive Applications on FPGAs with HLS
FPGAs have become emerging computing infrastructures for accelerating ap...
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04/08/2021
Software/Hardware Co-design for Multi-modal Multi-task Learning in Autonomous Systems
Optimizing the quality of result (QoR) and the quality of service (QoS) ...
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03/25/2021
Enabling Design Methodologies and Future Trends for Edge AI: Specialization and Co-design
Artificial intelligence (AI) technologies have dramatically advanced in ...
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03/04/2021
Large Graph Convolutional Network Training with GPU-Oriented Data Communication Architecture
Graph Convolutional Networks (GCNs) are increasingly adopted in large-sc...
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01/20/2021
PyTorch-Direct: Enabling GPU Centric Data Access for Very Large Graph Neural Network Training with Irregular Accesses
With the increasing adoption of graph neural networks (GNNs) in the mach...
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12/22/2020
FracBNN: Accurate and FPGA-Efficient Binary Neural Networks with Fractional Activations
Binary neural networks (BNNs) have 1-bit weights and activations. Such n...
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10/14/2020
Effective Algorithm-Accelerator Co-design for AI Solutions on Edge Devices
High quality AI solutions require joint optimization of AI algorithms, s...
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08/28/2020
DNNExplorer: A Framework for Modeling and Exploring a Novel Paradigm of FPGA-based DNN Accelerator
Existing FPGA-based DNN accelerators typically fall into two design para...
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05/18/2020
VecQ: Minimal Loss DNN Model Compression With Vectorized Weight Quantization
Quantization has been proven to be an effective method for reducing the ...
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05/18/2020
HaoCL: Harnessing Large-scale Heterogeneous Processors Made Easy
The pervasive adoption of Deep Learning (DL) and Graph Processing (GP) m...
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05/06/2020
EDD: Efficient Differentiable DNN Architecture and Implementation Co-search for Embedded AI Solutions
High quality AI solutions require joint optimization of AI algorithms an...
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04/08/2020
HybridDNN: A Framework for High-Performance Hybrid DNN Accelerator Design and Implementation
To speedup Deep Neural Networks (DNN) accelerator design and enable effe...
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02/27/2020
Compressing Large-Scale Transformer-Based Models: A Case Study on BERT
Transformer-based models pre-trained on large-scale corpora achieve stat...
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01/06/2020
AutoDNNchip: An Automated DNN Chip Predictor and Builder for Both FPGAs and ASICs
Recent breakthroughs in Deep Neural Networks (DNNs) have fueled a growin...
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11/18/2019
NAIS: Neural Architecture and Implementation Search and its Applications in Autonomous Driving
The rapidly growing demands for powerful AI algorithms in many applicati...
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09/20/2019
SkyNet: a Hardware-Efficient Method for Object Detection and Tracking on Embedded Systems
Developing object detection and tracking on resource-constrained embedde...
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08/04/2019
Analysis and Optimization of I/O Cache Coherency Strategies for SoC-FPGA Device
Unlike traditional PCIe-based FPGA accelerators, heterogeneous SoC-FPGA ...
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06/25/2019
SkyNet: A Champion Model for DAC-SDC on Low Power Object Detection
Developing artificial intelligence (AI) at the edge is always challengin...
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05/20/2019
A Bi-Directional Co-Design Approach to Enable Deep Learning on IoT Devices
Developing deep learning models for resource-constrained Internet-of-Thi...
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04/09/2019
FPGA/DNN Co-Design: An Efficient Design Methodology for IoT Intelligence on the Edge
While embedded FPGAs are attractive platforms for DNN acceleration on ed...
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11/05/2018
When CTC Training Meets Acoustic Landmarks
Connectionist temporal classification (CTC) training criterion provides ...
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07/31/2018
Design Flow of Accelerating Hybrid Extremely Low Bit-width Neural Network in Embedded FPGA
Neural network accelerators with low latency and low energy consumption ...
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05/15/2018
Improved ASR for Under-Resourced Languages Through Multi-Task Learning with Acoustic Landmarks
Furui first demonstrated that the identity of both consonant and vowel c...
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03/23/2018
Face Recognition with Hybrid Efficient Convolution Algorithms on FPGAs
Deep Convolutional Neural Networks have become a Swiss knife in solving ...
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03/06/2018
ASAP: Accelerated Short-Read Alignment on Programmable Hardware
The proliferation of high-throughput sequencing machines ensures rapid g...
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02/27/2018
CSRNet: Dilated Convolutional Neural Networks for Understanding the Highly Congested Scenes
We propose a network for Congested Scene Recognition called CSRNet to pr...
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10/27/2017
Acoustic Landmarks Contain More Information About the Phone String than Other Frames for Automatic Speech Recognition with Deep Neural Network Acoustic Model
Most mainstream Automatic Speech Recognition (ASR) systems consider all ...
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10/27/2017
